Programa de Doctorat en Arquitectura de Computadors: Enviaments recents
Ara mostrant els elements 161-180 de 260
Soft error mitigation techniques for future chip multiprocessors
The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for ...
The MPI/OmpSs parallel programming model
Even today supercomputing systems have already reached millions of cores for a single machine, which are connected by using a complex network interconnection. Reducing communication time across processes becomes the most ...
Reliability for exascale computing : system modelling and error mitigation for task-parallel HPC applications
As high performance computing (HPC) systems continue to grow, their fault rate increases. Applications running on these systems have to deal with rates on the order of hours or days. Furthermore, some studies for future ...
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
Critical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) ...
Novel vector architectures for data management
As the rate of annual data generation grows exponentially, there is a demand to manage, query and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. ...
Co-designed solutions for overhead removal in dynamically typed languages
Dynamically typed languages are ubiquitous in today's applications. These languages ease the task of programmers but introduce significant runtime overheads since variables are neither declared nor bound to a particular ...
Statistical analysis and design of subthreshold operation memories
This thesis presents novel methods based on a combination of well-known statistical techniques for faster estimation of memory yield and their application in the design of energy-efficient subthreshold memories. The emergence ...
Energy sharing in smart grids : a game theory approach
The need for energy conservation, grid reliability, and improved operational efficiencies have led to the changes from conventional electricity grids which have “blind” and manual operations, along with the electromechanical ...
Broadcast-oriented wireless network-on-chip : fundamentals and feasibility
Recent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number ...
In-operation planning in flexgrid optical core networks
New generation applications, such as cloud computing or video distribution, can run in a telecom cloud infrastructure where the datacenters (DCs) of telecom operators are integrated in their networks thus, increasing ...
Orchestrating datacenters and networks to facilitate the telecom cloud
In the Internet of services, information technology (IT) infrastructure providers play a critical role in making the services accessible to end-users. IT infrastructure providers host platforms and services in their ...
Per-task energy metering and accounting in the multicore era
Chip multi-core processors (CMPs) are the preferred processing platform across different domains such as data centers, real-time systems and mobile devices. In all those domains, energy is arguably the most expensive ...
Improving the performance and energy-efficiency of virtual memory
Virtual memory improves programmer productivity, enhances process security, and increases memory utilization. However, virtual memory requires an address translation from the virtual to the physical address space on every ...
Multicore architecture prototyping on reconfigurable devices
In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which ...
Scalable community detection for social networks
Many applications can be modeled intuitively as graphs, where nodes represent the entities and the edges the relationships between them. This way, we are able to better understand them and how they interact. One particularity ...
Circuit designs for increasing reliability and reducing energy
Computing technology has witnessed an inimitable progress in the last decades which is the result of CMOS technology scaling commensurate with Moore's law. Transistor feature sizes have shrunk to half at each generation, ...
Memory architectures for exaflop computing systems
Most computing systems are heavily dependent on their main memories, as their primary storage, or as an intermediate cache for slower storage systems (HDDs). The capacity of memory systems, as well as their performance, ...
An approach to pervasive monitoring in dynamic learning contexts : data sensing, communication support and awareness provision
It is within the capabilities of current technology to support the emerging learning paradigms. These paradigms suggest that today’s learning activities and environments are pervas ive and require a higher level of dynamism ...
Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
The worldwide utilization of mobile devices makes the segment of low power mobile processors leading in the entire computer industry. Customers demand low-cost, high-performance and energy-efficient mobile devices, which ...
Identifying and combating cyber-threats in the field of online banking
This thesis has been carried out in the industrial environment external to the University, as an industrial PhD. The results of this PhD have been tested, validated, and implemented in the production environment of Caixabank ...
