Programa de Doctorat en Arquitectura de Computadors: Envíos recientes
Mostrando ítems 141-160 de 260
Simulation methodologies for future large-scale parallel systems
Since the early 2000s, computer systems have seen a transition from single-core to multi-core systems. While single-core systems included only one processor core on a chip, current multi-core processors include up to tens ...
Memory hierarchies for future HPC architectures
Efficiently managing the memory subsystem of modern multi/manycore architectures is increasingly becoming a challenge as systems grow in complexity and heterogeneity. In the field of high performance computing (HPC) in ...
Edge-elements formulation of 3D CSEM in geophysics : a parallel approach
Electromagnetic methods (EM) are an invaluable research tool in geophysics whose relevance has increased rapidly in recent years due to its wide industrial adoption. In particular, the forward modelling of three-dimensional ...
Enabling the use of embedded and mobile technologies for high-performance computing
In the late 1990s, powerful economic forces led to the adoption of commodity desktop processors in High-Performance Computing(HPC). This transformation has been so effective that the November 2016 TOP500 list is still ...
Enabling caches in probabilistic timing analysis
Hardware and software complexity of future critical real-time systems challenges the scalability of traditional timing analysis methods. Measurement-Based Probabilistic Timing Analysis (MBPTA) has recently emerged as an ...
Query expansion by relying on the structure of knowledge bases
Query expansion techniques aim at improving the results achieved by a user's query by means of introducing new expansion terms, called expansion features. Expansion features introduce new concepts that are semantically ...
Energy optimising methodologies on heterogeneous data centres
In 2013, U.S. data centres accounted for 2.2% of the country's total electricity consumption, a figure that is projected to increase rapidly over the next decade. A significant proportion of power consumed within a data ...
Forwarding fault detection in wireless community networks
Wireless community networks (WCN) are specially vulnerable to routing forwarding failures because of their intrinsic characteristics: use of inexpensive hardware that can be easily accessed; managed in a decentralized way, ...
On algorithmic reductions in task-parallel programming models
Wide adoption of parallel processing hardware in mainstream computing as well as the interest for efficient parallel programming in developer communities increase the demand for programming models that offer support for ...
Dynamic load balancing for hybrid applications
It is well known that load imbalance is a major source of efficiency loss in HPC (High Performance Computing) environments. The load imbalance problem has very different sources, from static ones related to the data ...
dataClay : next generation object storage
Existing solutions for data sharing are not fully compatible with multi-provider contexts. Traditionally, providers offer their datasets through hermetic Data Services with restricted APIs. Therefore, consumers are compelled ...
Towards multiprogrammed GPUs
Programmable Graphics Processing Units (GPUs) have recently become the most pervasitheve massively parallel processors. They have come a long way, from fixed function ASICs designed to accelerate graphics tasks to a ...
Design of energy-efficient vector units for in-order cores
In the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all computer systems. Technology feature size scaling leads to higher power density and therefore to complex and ...
On the design of power- and energy-efficient functional units for vector processors
Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting datalevel parallelism. While vector processors succeeded in the high performance ...
Improving prefetching mechanisms for tiled CMP platforms
Recently, high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures to deal with instruction level parallelism limitations and, more important, to manage the power consumption that is ...
Performance-aware energy optimizations in networks for HPC
Energy efficiency is an important challenge in the field of High Performance Computing (HPC). High energy requirements not only limit the potential to realize next-generation machines but are also an increasing part of the ...
Improving the efficiency of multicore systems through software and hardware cooperation
Increasing processors' clock frequency has traditionally been one of the largest drivers of performance improvements for computing systems. In the first half of the 2000s, however, it became clear that continuing to increase ...
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors
As the transistor budgets outpace the power envelope (the power-wall issue), new architectural and microarchitectural techniques are needed to improve, or at least maintain, the power efficiency of next-generation processors. ...
A multicore emulator with a profiling Infrastructure for transactional memory on FPGA
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory ...
Decoupling state from control in software-defined networking
Software-Defined Networking (SDN) arose as a solution to address the limitations of traditional networking. In SDN networks, the control-plane is decoupled from the data-plane devices and logically centralized in a new ...
